1. Field of the Invention
The present invention relates to a semiconductor chip and a semiconductor chip manufacturing method.
2. Discussion of the Background
FIG. 43 shows a conventional semiconductor chip 330 and a mounting state thereof. A solder 344 forming a bump 310 is provided on the aluminum electrode pad 332 of the semiconductor chip 330 through a nickel plated layer 334 and a gold plated layer 338. Here, the semiconductor chip 330 is electrically connected to an electrode pad 352 on a package 350 side through the bump 310.
Meanwhile, due to the difference in coefficient of thermal expansion between the semiconductor chip 330 and the package 350, it is necessary to relax a stress generated between the semiconductor chip 330 and the package 350. In a mounting state shown in FIG. 43, an under-fill 336 is provided between the semiconductor chip 330 and the package 350 to fixedly attach them, thereby avoiding the concentration of a stress on a electrical connection section to prevent the occurrence of a break on the electrical connection sections.
However, following the recent high integration of semiconductor chips, the bumps of a semiconductor chip become smaller in size. In the mounting state described above, too, the electrical connection section thus made small in size is sometimes broken due to the stress between the semiconductor chip 330 and the package 350.
To address such a problem, there is proposed forming a flexible copper post on the aluminum electrode pad 332 through a barrier metal film and allowing the post to absorb the stress generated between the semiconductor chip 330 and the package. However, the barrier metal film formed by sputtering which is normally used, is not only inferior in productivity but also has a residual stress and adversely affects the function of the semiconductor chip in the vicinity of the aluminum electrode pad. Due to this, it is difficult to apply the above proposal to a semiconductor chip having an area pad type aluminum electrode pad formed thereon.
According to one aspect of the present invention, a semiconductor chip includes a copper plated member. A copper plated member is formed on and electrically connected to a surface of an aluminum electrode pad through a nickel-copper composite layer. The surface of the aluminum electrode pad is subjected to a zincate treatment.
According to another aspect of the present invention, a semiconductor chip includes an aluminum electrode pad which is provided on a chip surface of the semiconductor chip and an electrode surface of which is subjected to a zincate treatment. A resin insulating layer is provided on the chip surface of the semiconductor chip and has a hole in which the electrode surface of the aluminum electrode pad locates. A nickel-copper composite layer is formed on and electrically connected to the surface of the aluminum electrode pad in the hole. A via is made of a copper plated member. The via is formed on and electrically connected to the nickel-copper composite layer in the hole.
According to the other aspect of the present invention, a semiconductor chip manufacturing method includes forming a resin insulating layer on a surface of a semiconductor chip on a side of an aluminum electrode pad. Then a hole is formed in the resin insulating layer to reach the aluminum electrode pad. A zincate treatment is conducted to the aluminum electrode pad at a bottom of the hole. Then a nickel-copper composite plated layer is formed on the aluminum electrode pad. A via made of a copper plated member is formed on the nickel-copper composite plated layer in the hole.
According to the further aspect of the present invention, a semiconductor chip manufacturing method includes conducting a zincate treatment to a surface of an aluminum electrode pad of a semiconductor chip. Then a nickel-copper composite plated layer is formed on the surface of an aluminum electrode pad. A resin insulating layer is formed on an aluminum electrode pad-side surface of the semiconductor chip. Then a hole is formed in the resin insulating layer to reach the nickel-copper composite plated layer. A via made of a copper plated member is formed on the nickel-copper composite plated layer in the hole.
According to yet another aspect of the present invention, a semiconductor chip manufacturing method includes conducting a zincate treatment to a surface of an aluminum electrode pad of a semiconductor chip. Then a nickel-copper composite plated layer is formed on the surface of the aluminum electrode pad. An an electroless copper plated layer is formed on an aluminum electrode pad-side surface of the semiconductor chip. A plating resist layer is formed on a surface of the electroless copper plated layer of the semiconductor chip. Then a hole is formed to reach the electroless copper plated layer. The hole is filled with a copper plated member to form a via. The plating resist layer is removed. Then an etching treatment is conducted to remove the electroless plated layer below the plating resist layer.
According to yet another aspect of the present invention, a semiconductor chip includes a first insulating layer, a conductor circuit layer and a second insulating layer which are build up in this order on an electrode pad side of the semiconductor chip. An inner via electrically connects the electrode pad of the semiconductor chip to the conductor circuit layer. The inner via is formed in said first insulating layer. The second insulating layer is a soft insulating layer and is provided with a hole reaching the conductor circuit layer. A filled via is made of a copper plated member in the hole. The electrode pad of the semiconductor chip is a zincate treated aluminum electrode. A copper plated member is formed on the electrode pad in the inner via through a nickel-copper composite plated layer.
According to yet another aspect of the present invention, a semiconductor chip manufacturing method includes forming a first insulating layer on an aluminum electrode pad-side surface of a semiconductor chip. Then forming a first hole reaching an aluminum electrode pad. A zincate treatment is conducted to the aluminum electrode pad at a bottom portion of the first hole. Then a nickel-copper composite plated layer is formed. An inside of the hole and a surface of the first insulating layer are copper-plated. An inner via and a conductor circuit layer are formed. The first insulating layer and the conductor circuit layer are covered with a soft resin. A second insulating layer is formed. A second hole is formed in the second insulating layer. The second hole reaches the conductor circuit layer. The second hole is filled with a copper plated member. A filled via is formed.
According to the other aspect of the present invention, a semiconductor chip manufacturing method includes conducting a zincate treatment to a surface of an aluminum electrode pad of a semiconductor chip. Then a nickel-copper composite plated layer is formed. A a first insulating layer is formed on an aluminum electrode pad-side surface of the semiconductor chip. Then a first hole reaching the nickel-copper composite plated layer is formed. An inside of the first hole and a surface of the first insulating layer are copper-plated. An inner via and a conductor circuit layer are formed. The first insulating layer and the conductor circuit layer are covered with a soft resin. A second insulating layer is formed. A second hole is formed in the second insulating layer. The second hole reaches the conductor circuit layer. The second hole is filled with a copper plated member. A filled via is formed.
According to the further aspect of the present invention, a semiconductor chip includes an electrode pad. A first insulating layer is formed on a surface of the semiconductor chip on a side of the electrode pad. A conductor circuit layer is formed on first insulating layer. A second insulating layer is formed on the first insulating layer and the conductor circuit layer. The second insulating layer is a soft insulating layer and is provided with a hole reaching the conductor circuit layer. An inner via is formed in the first insulating layer and electrically connects the electrode pad to the conductor circuit layer. A filled via is formed in the second insulating layer and includes an electroless copper plated layer formed on a bottom portion and a wall surface of the hole in which a resin is filled.
According to the other aspect of the present invention, a semiconductor chip manufacturing method includes forming a first insulating layer on an aluminum electrode pad-side surface of a semiconductor chip. Then a first hole reaching an aluminum electrode pad is formed. A zincate treatment is conducted to the aluminum electrode pad on a bottom portion of the first hole. Then a nickel-copper composite plated layer is formed. An inside of the first hole and a surface of the first insulating layer are copper-plated.
An inner via and a conductor circuit layer are formed. The first insulating layer and the conductor circuit layer are covered with a soft resin. A second insulating layer is formed. A second hole is formed in the second insulating layer. The second hole reaches the conductor circuit layer. An electroless copper plated layer is formed on a bottom portion and a wall surface of said second hole. Then a resin is filled in the electroless copper plated layer. A filled via is formed.
According to yet further aspect of the present invention, a semiconductor chip manufacturing method includes conducting a zincate treatment to a surface of an aluminum electrode pad of a semiconductor chip. Then a nickel-copper composite plated layer is formed. A first insulating layer is formed on an aluminum electrode pad-side surface of the semiconductor chip. Then a first hole reaching the nickel-copper composite plated layer is formed. An inside of the first hole and a surface of the first insulating layer are copper-plated. An inner via and a conductor circuit layer are formed. The first insulating layer and the conductor circuit layer are covered with a soft resin. A second insulating layer is formed. A second hole is formed in the second insulating layer. The second hole reaches the conductor circuit layer. An electroless copper plated layer is formed on a bottom portion and a wall surface of said second hole. Then a resin is filled in the electroless copper plated layer. A filled via is formed.